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India on Wednesday (27 April) announced 'Digital India RISC-V Microprocessor Programme (DIR-V)' with an overall aim to enable creation of next-gen microprocessors in India for the world and achieve industry-grade silicon and design wins by December 2023, an official release said.

The programme was announced by Union Minister of State for Ministry of Electronics and Information Technology Rajeev Chandrasekhar.

IIT Madras director Professor V Kamakoti will be the Chief Architect of the DIRV-Programme while C-DAC's S Krishnakumar Rao will be the Programme Manager.

The minister unveiled the blueprint of the roadmap of design and implementation of the DIR-V Programme with – SHAKTI Processor by IIT Madras and VEGA Processor by C-DAC.

He also unveiled the strategic Roadmap for India's Semiconductor Design and Innovation to catalyse the semiconductor ecosystem in the country.

While setting the aggressive milestones for commercial silicon of SHAKTI & VEGA processors and their design wins by December 2023, Rajeev Chandrasekhar mentioned that DIR-V will see partnerships between startups, academia and multinationals, to make India not only a RISC-V talent hub for the world but also supplier of RISC-V SoC (System on Chips) for Servers, Mobile devices, Automotive, IoT and Microcontrollers across the globe, the ministry said in a release.

Reminiscing his early days as x-86 processor chip designer at Intel, Rajeev Chandrasekhar said that many new processor architectures have gone through an initial period of ferment characterised by waves of innovations.

At some point, however, they all settled on a dominant design. ARM and x-86 are two such instruction set architectures- one of which is licensed and other is sold, where industry consolidated in earlier decades, he said.

However, RISC-V has emerged as a strong alternative to them in last decade, having no licensing encumbrances, enabling its adoption by one and all in semiconductor industry, at different complexity levels for various design purposes.

Challenging the status quo, RISC-V Instruction Set Architecture (ISA) is not only witnessing a quantum leap and unprecedented levels of processor innovation owing to its free and open nature but also pushing the Moore’s Law beyond its limits.

Today, there is a thriving ecosystem of chip designers at academia, scientific societies and startups in the country, contending to gain the market share in RISC-V growing market.

While India has certainly taken several early steps in processor design area, the time is felicitous now to advocate India’s strides in RISC-V global community and unveil the Digital India RISC-V Processor roadmap to the world, he said.

He announced that the the Ministry of Electronics and IT is planning to join the RISC-V International as Premiere Board Member to collaborate, contribute and advocate India’s expertise with other global RISC-V leaders.

Intel Foundry Services (IFS) VP Bob Brennan, while speaking about the IFS innovation fund announced by the US tech giant to support early-stage startups and established firms building technology for the foundry ecosystem, appreciated the Indian RISC-V movement.

IIT Madras director Professor V Kamakoti, while highlighting the Intel's support for getting fabricated 22nm SHAKTI Chip at Intel foundry, mentioned that DIR-V Program will catalyse the design innovation in the country and will encourage the several domestic startups working in RISC-V domains like- micro architecture design, verification and security aspects.

RISC-V International CEO Calista Redmond highlighted the profound technical collaboration in RISC-V community by IIT Madras, one of five honored RISC-V Development partners.

She also congratulated C-DAC for designing a range of RISC-V processors and InCore Semiconductors for releasing the Open-Source RISC-V Core Verification tool.